Chipsun Knowledge | Key Points of Crystal Oscillators in PCB Design
IC circuit design, the clock frequency of the system crystal oscillator is very high, and the energy of the interfering harmonics is also strong. In addition to being conducted through the input and output lines, the harmonics will also radiate from the space. This leads to strict requirements for the layout of the crystal oscillator in PCB design. If there is a mistake, it will easily cause strong spurious radiation problems, which are difficult to solve by other methods. Therefore, the layout of the crystal oscillator and CLK signal lines is crucial during PCB board layout.
Layout and Routing Design
The crystal oscillator contains a quartz crystal inside. If it is accidentally dropped or hit by an unknown impact, the quartz crystal is prone to fracture and damage. Therefore, the crystal oscillator should be placed away from the board edge and close to the MCU.
The crystal oscillator should be adjacent to the clock input pin of the main control chip (such as MCU, FPGA), with a maximum routing length ≤ 10mm.
Figure 1: Schematic diagram of crystal oscillator layout (no text on the image, so no translation required)
Keep away from high-speed signal lines (such as DDR, USB differential pairs) with a spacing ≥ 3 times the line width to avoid crosstalk.
Routing Length and Width
Clock routes should be as short and straight as possible. The line width should be appropriately thickened to reduce impedance, but the distance from heat sources needs to be balanced. For high-frequency signals (such as above 10 MHz), the routing length should be controlled within 500 mils.
Ground Shielding
It is recommended to adopt ground shielding for clock routes, surrounding the signal lines with ground lines, and drilling vias to connect to the ground layer at intervals (such as 100 mils) to enhance anti-interference capability.
Avoid Cross Interference
The output signal line of the crystal oscillator must not cross the power layer or sensitive signal lines. If crossing is necessary, the routing should be vertical and a spacing should be maintained.
Decoupling and Filtering
Power Decoupling
A decoupling capacitor (such as a 100nF ceramic capacitor) should be added to the power pin of the crystal oscillator and placed close to the pin to filter out high-frequency noise. For active crystal oscillators, a small resistor (47~100 Ω) can be connected in series with the power line for current limiting.
Load Capacitor Configuration
Passive crystal oscillators require external load capacitors (Cg and Cd), whose values must satisfy: Load Capacitance CL = (Cg × Cd) / (Cg + Cd) + Stray Capacitance (Cs). The stray capacitance is usually 2~5 pF. During design, the values of Cg and Cd should be adjusted according to the crystal oscillator specifications (for example, when CL=15 pF, Cg=Cd=24 pF can be taken).
The coupling capacitor should be placed as close as possible to the power pin of the crystal oscillator. If there are multiple coupling capacitors, they should be arranged in descending order of capacitance value according to the power inflow direction; the crystal oscillator should be as close as possible to the MCU.
Other Notes
High Independence
Ensure that there are no other components around the crystal oscillator as much as possible to prevent mutual interference between devices, which will affect the quality of the clock and other signals. No components are allowed to be placed within 1mm around the crystal oscillator, and no via routing is allowed within 0.5mm. No vias (including ground vias) are drilled under all crystal oscillators. Be careful with the routing of the crystal oscillator and ground.
Arrange other clock lines and frequently switching signal lines as far away from the crystal oscillator connections as possible.
Shell Grounding
The shell of the crystal oscillator must be grounded. In addition to preventing the crystal oscillator from radiating outward, it can also shield external interference.
Document Description
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